Integrated circuit (IC) devices typically include one or more IC dice mounted on a substrate and housed in a protective package made of suitable material such as plastic, ceramic or metal. There are several package types including ball grid arrays (BGAs), pin grid arrays (PGAs), plastic leaded chip carriers, and plastic quad flat packs. Each of the package types is typically available in numerous sizes and configurations. The package type and configuration selected by an IC manufacturer for a particular IC chip may be determined by the size and complexity of the IC chip and/or in accordance with a customer's requirements.
For example, in a BGA package, an integrated circuit (IC) die or chip having a plurality of bonding pads formed on an active surface thereof is typically mounted on a top surface of a substrate. The substrate has a plurality of conductive traces that are connected (for example, by wire bonding, tape automated bonding, or flip-chip bonding) to corresponding bonding pads of the IC die. An array of solder balls (typically arranged in a rectangular grid) is formed on the bottom surface of the substrate (e.g., opposite the surface to which the IC die is mounted). The substrate includes various interconnection layers (e.g., power plane, ground plane, and signal lines) and vias that provide electrical paths between the conductive traces on the top surface of the substrate and corresponding solder balls formed on the bottom surface of the substrate. The package is typically placed on a printed wiring board, and heated to reflow the solder balls on the bottom surface of the substrate to form connections between the IC die and elements on the printed wiring board.
To reduce manufacturing costs, many IC manufacturers use a standard substrate to accommodate different variations of an IC chip, or a family of similar chips. Typically, the standard substrate includes a predetermined number of solder balls and corresponding conductive traces that can be electrically connected to the bonding pads of an IC die that is mounted on the substrate. Because the standard substrate can be used to receive IC dice having different numbers of bonding pads, for any given package, the number of bonding pads on the IC die may be less than the number of conductive traces and solder balls formed on the substrate. As a result, some of these IC packages may include one or more “extra” solder balls that are not connected to any of the bonding pads formed on the mounted IC die. These extra solder balls are commonly referred to as “no-connect pins.”
For example, FIGS. 1A-1C show simplified top, bottom, and sectional views, respectively, of a typical BGA package 100. BGA package 100 includes an IC chip or die 110 mounted on a top surface 120t of a substrate 120. A plurality of conductive bonding pads 111 formed on an active surface 110a of die 110 are connected to corresponding conductive traces 121, 122, and 123 formed on substrate 120 via wire bond connections 112. Substrate 120, which is made of a suitable dielectric material such as resin or epoxy, includes a plurality of land pads 124 formed on its bottom surface 120b, and includes a well-known interconnect structure including embedded metal layers 128b and 128c for providing power planes (e.g., VDD and VSS) and including conductive vias 125 for providing conductive paths between land pads 124 and corresponding bonding pads 111 of die 110 through conductive traces 123. Solder balls 140 mounted to corresponding land pads 124 provide electrical connections between package 100 and other external devices or systems (not shown for simplicity). Note that in the simplified illustrations of FIGS. 1A-1C, package 100 is shown to include 25 solder balls 140, and die 110 is shown to include 14 bonding pads 111. Thus, because the number of solder balls 140 is greater than the number of die pads 111 for the exemplary IC package 100, a number of solder balls 140 such as solder ball 140d are not connected to any corresponding bonding pads 111 of die 110, and are thus designated as NC pins.
For purposes of discussion herein, solder balls 140a and 140e are active pins that provide signals to and from die 110, solder balls 140b and 140c are power pins that provide supply voltages (e.g., VDD and VSS) to die 110, and solder ball 140d is an NC pin. For example, signals are transmitted between active solder ball 140a and corresponding active die pad 111a through bonding wire 112a, conductive trace 123a, conductive via 125a, and land pad 124a, and signals are transmitted between active solder ball 140e and corresponding active die pad 111e through bonding wire 112e, conductive trace 123e, conductive via 125e, and land pad 124e. A first voltage supply such as VDD is provided from power pin 140b to corresponding die pad 111b through land pad 124b, power plane 128b, conductive via 125b, conductive trace 122, and bonding wire 112b. A second voltage supply such as VSS is provided from power pin 140c to corresponding die pad 111c through land pad 124c, conductive via 125c, power plane 128c, conductive trace 121, and bonding wire 112c. 
As mentioned above, solder ball 140d is an NC pin. Together, land pad 124d of the NC pin 140d and metal layer 128c form a capacitor that can store an undesirable accumulation of charge in the dielectric material 150 surrounding the NC pin 140d. Because there is no circuit connection to the NC pin's land pad 124d, the charge accumulation in dielectric area 150 can result in an undesirable voltage arc to adjacent active pins, such as active pin 140e, that can damage the IC package. For example, applying a test voltage to the NC pin 140d during quality test operations can result in undesirable charge accumulation in the dielectric material 150 surrounding NC pin 140d, which in turn can cause a damaging voltage arc to nearby pins. Further, during handling of package 100 by humans, electrostatic discharge (ESD) associated with a phenomenon commonly known as human body model (HBM) stress can result in charge accumulation surrounding the NC pin 140d, which as described above can cause a damaging voltage arc to nearby pins.
One solution to the ESD problem with NC pins in IC packages such as BGA package 100 is to avoid testing the no-connect pins for ESD susceptibility prior to delivery. However, although standards commissions such as JEDEC currently do not require such testing of NC connect pins, it is likely that future ESD specifications will require the no-connect pins to be tested for ESD susceptibility. Further, avoiding the application of a test probe to NC pins during testing operations does not prevent charge accumulation around the NC pin caused by HBM ESD during handling of the IC package. Another solution is to selectively connect the no-connect pins to ESD protection circuitry (not shown for simplicity) provided within the IC die. However, providing ESD protection circuitry for NC pins in the IC die, as well as including circuitry that can selectively connect the NC pins to the ESD protection circuitry, undesirably increases chip size and complexity.
As more and more solder balls (or pins) are provided on IC packages to achieve greater packing densities, the distance between the pins decreases, which exacerbates ESD problems associated with the NC pins. Therefore, there is a need to provide ESD protection for an IC package's NC pins without including ESD circuitry that increases IC chip size and complexity.